1. Technical Field
The invention disclosed herein relates to a semiconductor package, and more particularly, to a stacked chip package having a plurality of vertically stacked semiconductor chips, and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor devices and their associated packaging techniques have been jointly developed in order to achieve high density and high speed in a thin, compact footprint. In a semiconductor package structure, the through hole mounting method has been replaced by a surface mounting method in order to drastically increase the mounting density of package structures for a given circuit substrate. A chip scale package (CSP) has been developed and continuously studied by various companies. The CSP maintains bare chip characteristics in a package state, can be easily handled, and has a considerably reduced package size. Additionally, a three dimensional stacking technique, which stacks a plurality of unit semiconductor chips or unit semiconductor chip packages to increase capacity and mounting density, has recently generated interest, and is actively being researched by the semiconductor manufacturing industry.
FIG. 1 is a sectional view of a conventional stacked chip package structure. Referring to FIG. 1, a semiconductor chip 5 is attached on another semiconductor chip 3, which is mounted on a substrate 1 having a circuit pattern, using an adhesive such as medium 6. Chip pads 3a and 5a of the semiconductor chips 3 and 5 and electrode pads 7 of the substrate 1 are electrically connected by a metal wire 4. The top of the substrate 1 including the semiconductor chips 3 and 5, and the metal wire 4 form a package body which may be covered using an epoxy molding resin (not shown). The epoxy molding resin protects the surfaces of the semiconductor chips 3 and 5 as well as the metal wires 4. The bottom of the substrate 1 includes a solder ball 9 which may be connected to an external circuit, such as would be found on a printed circuit board (PCB).
In a conventional stacked chip package having the above structure, the semiconductor chips 3 and 5 and the substrate 1 have to be electrically connected to each other through the metal wires 4, typically by a wire bonding process. Specifically, the chip pads 3a and 5a and the electrode pads 7 in the substrate 1 need to be electrically connected, or wire bonded. It may take several processing steps to make all of the wire bonding connections. Therefore, it takes a long processing time to make the conventional stacked chip package. Moreover, it is difficult to reduce the packaging area because a pre-defined wire loop shape needs to be obtained for ensuring reliable processing and operational performance. If the loop in metal wire 4 is not formed in the correct shape and correct height, wire 4 may be disconnected from the chip pads 3a and 5a during subsequent processing or during operation. Since the loops in metal wires 4 extend significantly above the top surface of the semiconductor chip 5, the overall height of the semiconductor package has to be increased so that the epoxy molding resin can adequately protect the metal wires 4. Especially, when the number of stacked chips increases, it is very difficult to reduce the package size and a short between the bonding wires of the several stacked packages can occur.
Further, several problems associated with wire bonding such as bending and protruding phenomena, incomplete filling of the epoxy molding resin, and an unstable electrical connection may occur in stacked chip packages using wire bonding, leading to deterioration of the reliability of the package. Consequently, a stacked semiconductor package that does not include bonding wires is desired.